1. Field
Exemplary embodiments of the present invention relate to nitride-based transistors having structures for suppressing leakage current.
2. Discussion of the Background
In the electronics industry, high voltage transistors operating at a high speed are increasingly in demand in view of the development of information and communication technologies. In response to such a demand, Group III-V compound semiconductor transistors, for example, gallium nitride (GaN) transistors have been proposed. GaN transistors may exhibit a relatively fast switching characteristic and a relatively high breakdown voltage characteristic as compared with the conventional silicon transistors. Thus, GaN transistors may be attractive as candidates for improving the performance of communication systems.
In general, GaN transistors may be fabricated to have a planar-type configuration or a vertical-type configuration. Each of the planar-type GaN transistors may include a source region, a channel region, and a drain region that are coplanar with each other. Thus, carriers may drift in a horizontal direction along a surface of the channel region. In such a case, there may be a limitation in improving the carrier mobility. This is because an electric field at a channel surface may disturb movement of the carriers. Further, when the planar-type GaN transistors operate, an electric field may be concentrated at corners of gate electrodes of the planar-type GaN transistors. This may lead to degradation of the breakdown voltage characteristic of the planar-type GaN transistors.
Vertical GaN transistors have been proposed to solve the above disadvantages. For example, current aperture vertical electron transistors (CAVETs) are taught in U.S. Patent Publication No. 2012/0319127 A1 to Chowdhury et al. According to Chowdhury, a source electrode and a drain electrode are disposed to vertically face each other, and a P-type gallium nitride (P-GaN) layer acting as a current blocking layer is disposed between the source and drain electrodes. Accordingly, a channel current may flow in a vertical direction from the drain electrode toward the source electrode through an aperture provided by the P-type gallium nitride (P-GaN) layer.
Meanwhile, defect sites may be formed at an interface between a nitride-based semiconductor layer acting as a body layer of the GaN transistors and a passivation layer or air corresponding to a heterogeneous material of the nitride-based semiconductor layer. The passivation layer may be an insulation layer such as a silicon oxide layer. The defect sites may trap or release electric charges to cause leakage current. This leakage current may degrade a high voltage characteristic of the GaN transistors. An annealing process performed at a temperature over 600 degrees Celsius has been used to reduce a density of the defect sites. However, in spite of the annealing process, there may be limitations in reducing the leakage current.